The present invention is generally within the field of integrated circuit (IC) device design and verification, and, more particularly, defines a new concept: package-level intellectual property (PLIP) embodied by a system and method for implementing the PLIP preverification for system on chip (SOC) devices. The SOC devices are very complex IC's that integrate tens of millions or hundreds of millions of transistors on single silicon chip.
To expedite the development of integrated circuits, chip designers typically combine standard cells from cell libraries. Cells may contain geometrical objects such as, for example, polygons (boundaries), paths, and other cells. Objects in the cell are assigned to “layers” of the design. Cells may be very simple structures that consist of a few transistors, or may be very complex structures that contain thousands or millions of transistors. The cells of the latter type are commonly referred to as “intellectual property” (IP), which represents a higher level of abstraction of a standard cell. Typically, IPs are provided by an IP vendor. As is illustrated by the process flow diagram of FIG. 1, an IP vendor develops and verifies each IP separately (blocks 102, 104), with the expectation that IC layouts that employ the IP will also meet specifications.
Practically speaking, an EP block is only viable if it takes less effort to integrate into an IC than it would to develop the block from scratch. Because IP blocks tend to be used as supplied (with no changes apart from those required by integration), functional verification of the IP block just by itself is less important, and has already been done during its development. Rather, the verification should be designed to show that the rest of the system correctly supports the IP block, and that its presence does not upset the other parts of the design.
Accordingly, an IC designer selects the cells or IPs it wishes to use in an IC layout to provide whatever structures or functionalities are required for a particular application. Each cell has one or more connectivity targets, which are predetermined points used to connect the patterns in a pair of cells. After the verification of the functional design of the cell selections in block 106 (e.g., synthesis by Register Transfer Level (RTL) simulations and translation of the RTL models to a SPICE (Simulation Program with Integrated Circuit Emphasis) netlist), the layout is submitted to a routing program (blocks 108, 110), which connects the target-containing patterns of the adjacent cells to form complete sets of patterns for each mask layer. When a design incorporates two cells adjacent to each other in an IC layout, the router identifies the location of the connectivity target in each cell, and constructs a connecting path between the targets, comprising one or more line segments. This connecting path is incorporated into the IC layout (block 112), so that the mask constructed from the connected cells includes continuous circuit paths.
Subsequently, the IC layout is submitted for artwork verification at block 114 (for example, using a program such as Calibre, by Mentor Graphics of Wilsonville, Oreg.). In the artwork verification process, compliance with design rules is checked. For example, the line spacing between each pair of adjacent lines is compared to the relevant minimum for that line. If the line spacing is less than the minimum required for the width of the merged line, a design rule violation is identified. Finally, cell-based IC design focuses on the package design and verification for the chip die (mechanical and electrical) as shown in block 116, 118.
More recently, complex SOC designs include existing, preverified IP libraries, as well as newly designed components. Depending upon the role of the IP in the SOC, certain IPs may be completely embedded inside the chip itself (i.e., no external connections to/from the die) while certain other fPs are used solely for communication of the signals of the SOC to the outside world. In the latter case, this type of IP continues to be operated at higher and higher signal rates (e.g., sub-gigabit per second to tens of gigabits per second). As such, the implementation and integration of this type of IP into an SOC presents significant challenges. Unfortunately, the two general types of existing implementable IPs (i.e., soft IP cores and hard IP cores) provide only a partial solution for IP integration and validation of complex SOCs, in terms of functionality, time to market, and profit. For example, conventional soft IP blocks are only validated up through the synthesizable RTL stage (blocks 102-104), while conventional hard IP blocks are only validated up through the GDS (Graphic Design Solutions) artwork stage (blocks 102-114).
Accordingly, it would be desirable to be able to provide an IP product that overcomes the existing integration and validation problems associated with present day SOC designs, such as (for example) those including mixed signal IPs therein.